Kaur, Amandeep

CMOS image sensors have drawn a lot of attention due to their superior performance in the past decade. The most demanding applications such as visual surveillance and intrusion detection in surveillance systems, and aerial monitoring in conflict zones, are made possible by recent technological advancements in near sensor-based systems. In the existing methodology, image sensors are being used along with a DSP processor to perform image classification and recognition. Continuously reading and transferring data of all pixels to CNN required high computation and power consumption of ADC. In this work, we propose a novel design for an intelligent CMOS image sensor wherein an analog Sobel edge detector is introduced before the ADC. Using the edge detector, instead of digitizing a natural image obtained off the sensor, only edges in the image are digitized and transferred for object classification and recognition tasks. This significantly reduces the power consumed by ADC as only edge-detected pixels are being converted into the digital domain. Analysis shows that object classification tasks on edge-detected images with reduced pixel information from thresholding operation result in pixel reduction by 67 %, 79 %, and 87 % for threshold values of 0.2, 0.3, and 0.4. This work shows that CNN models can still be trained with acceptable accuracy on state-of-the-art models and can reduce operating power for Intelligent edge devices.

A compressive acquisition technique for on-array image compression is proposed in this paper. It capitalizes on representation ability of accumulated spatial gradients of the acquired scene. The local variations inferred from strength of the accumulated gradients are used as cues to vary number of samples read through the image sensor readout. Such sampling enables the reconstruction using traditional interpolation techniques with desired quality. The proposed method is first verified using MATLAB simulations, where on an average, a compression of 87% is achieved, for a threshold of 40 intensity levels. The images are reconstructed using nearest neighbour interpolation (NNI) method which results in a mean peak signal to noise ratio (PSNR) value of 29.09 dB. The reconstructed images are further enhanced using deep convolutional neural network, which improves the PSNR to 32.46 dB. The biggest advantage of the proposed technique is low-complex hardware design. As a proof of concept, a hardware implementation of the technique is performed using discrete components. Pixel intensity values of standard images are converted into analog voltages using a data acquisition system and mapped in the input voltage range of 1.5 V -5.5 V. For a threshold of 3.8 V, the compression of 81% - 83% is observed for the considered images. The proposed technique is simple and effective, and is suitable for low-power complementary metal oxide semiconductor (CMOS) image sensors.

A 12-bit, programmable hybrid ADC for CMOS image sensor is proposed in this paper. The hybrid ADC internally uses cyclic-SAR architecture and results in an area efficient and high speed design. To minimize the total column ADC area, the elements of cyclic ADC are reused for SAR operation. The 12-bit programmable ADC can be operated either in high resolution mode or high speed mode depending on the number of bits allocated per stage. The prototype CMOS image sensor is designed and fabricated in AMS 350 nm CMOS OPTO process. A three-transistor pixel architecture followed by column parallel-readout circuit is implemented in a 9 µm column pitch. A prototype 128 × 96 image sensor consumes 62.7 mW of power at 3.3 V power supply.

In this paper, a low-power readout using reconfigurable cyclic ADC for CMOS image sensors is proposed. It reduces the total number of pixels to be read by taking advantage of pixel correlation. The required number of ADC operations is reduced, resulting in power saving. In contrast to the existing pixel correlation-based approaches, which focus only on the intensity differences, in the proposed method, the polarity of the differences is also taken into account. It helps in preserving fine edges representing features such as texture. The discarded or unread pixels are interpolated on-chip while reconfiguring the ADC input range according to the interpolation step size. Furthermore, this reduces the number of ADC conversion cycles by 25% to 50% for interpolation steps of 16 LSB and 64 LSBs, respectively. The ADC is designed and fabricated in UMC 180-nm CMOS technology, and the proposed method is verified for standard test images. The reconstructed images incorporating ADC non-linearities result in average Pratt's FoM values of 0.88, 0.86, and 0.81 for 60%, 70%, and 74% compression, respectively. The corresponding best values achieved by the existing approaches are 0.86, 0.80, and 0.77, respectively. The improvement in FoM is observed due to the consideration of polarity information. The proposed technique results from 33% to 50% power saving for 80% compression in 512times512 image, using reconfigurable ADC. Therefore, it is suitable for a power efficient CMOS sensor design.

Bio-signals such as electroencephalogram (EEG) contain low activity regions often called B-noise and high activity regions called active potentials. The high activity regions are more important as compared to their counterpart. In addition, the signals are considerably sparse in the low activity regions. Thus a full n-bit conversion of low activity samples into digital domain increases readout power and reduces data acquisition rate of analog to digital converter (ADC). To alleviate these problems, a reconfigurable cyclic ADC is presented in this paper. Input range and conversion cycles of the proposed ADC are varied according to the samples of the neural signal. The high activity region samples are resolved using conventional n-bits, however, the low activity region is resolved using less number of bits. This saves readout power and also reduces the digital data content. The proposed ADC is designed and fabricated in UMC 180 nm CMOS technology. The ADC operates at a sampling rate of 200 kS/s and consumes 61.8 μW of power. The chip occupies an area of 0.031 mm2. Using reconfiguration, the power saving of 28.6% is achieved compared to the conventional n-bit full conversion.

Obtaining a good quality image from a CMOS Image Sensor (CIS) is always a constraint due to the effect of noise present within the image sensor system. One of the dominant source of noise in CIS with column-parallel readout is Fixed Pattern Noise (FPN) which significantly degrade the image quality. This work implements an architecture for the reduction of vertical FPN called Fixed Pattern Noise Reduction Network (FPNrNet), which uses a Convolutional Neural Network (CNN) with an attention mechanism. The denoising performance of the FPNrNet model is quite similar to that of standard denoising models; however, a significant reduction in model size is observed due to a reduction in the number of parameters. An average Peak Signal-to-Noise Ratio (PSNR) improvement of around 11.3 dB with respect to input noisy image and an average Structural Similarity Index Measure (SSIM) of 0.99 is observed for Pascal VOC 2012 dataset. Further, the model is quantized on different bit precision using the Qkeras library and synthesized using the High-Level Synthesis for Machine Learning (hls4ml) platform to make it hardware friendly so that inference can be performed on resource-constrained edge devices.

This work proposes a single capacitor-based offset reduction technique for dynamic comparators. It additionally uses only one capacitor and two transistors to reduce the offset introduced due to threshold mismatch, resulting in an energy-efficient design. The proposed technique reduces the offset by four to six times compared to the conventional design for the entire input range. The comparator is designed in 65 nm CMOS process using 1.2 V power supply. It occupies an area of 21.2μm × 16μm. The performance of comparator is verified using post-layout simulations. The maximum operating frequency of comparator is 2 GHz and it consumes 51 fJ of energy per conversion cycle. The Monte-Carlo simulations performed for 500 samples result in worst-case offset of 1.7 mV.

CMOS image sensors have gained popularity due to low power consumption, high speed and their ability to scale to smaller sizes. These factors can further be improved by either improving the circuitry of the imager or by enhancing the processing capabilities of the entire imaging system through on-chip processing of the pixel information. One such improvement is to read only a small fraction of the pixel array information and reconstruct the original information from it. The on-chip prediction of the unread pixels to reconstruct the acquired image is still an open problem. Here we propose a solution to the problem which relies on on-chip implementation of simple convolutional neural network (CNN) for pixel prediction and image reconstruction. The system strives to selectively read only a minimal number of pixels (10% to 15%), while skipping the rest. This attributes to a considerable saving on power and checks the issue of latency at the ADC. This selective process in reading of only few pixels generates a sparse image signal. The proposed network is trained to reconstruct the estimation of the actual image from the sparse set. The hardware accelerator that incorporates the CNN model also considers hardware limitations and constraints such as power consumption and latency. The PSNR achieved for the SiDCNet variant with SqueezeNet achieves for test images is \sim30dB for 85% of pixels skipped, and the quantized model does not lose much in PSNR.

An input folding cyclic ADC for column-parallel readout in CMOS image sensor is proposed. A double sampling circuit in the CMOS image sensor is reused to perform input folding operation in cyclic ADC. In addition, a push-pull configuration based slew rate enhancement technique is used to reduce the settling time of multiplying digital to analog converter. The ADC results in a conversion rate of 1.38 MS/s while consuming 560 muW of power. A prototype CMOS image sensor, with 12-bit column-parallel cyclic ADC, is designed and fabricated in AMS 350 nm CMOS OPTO process at 3.3 V power supply. For a 96times 64 pixel array, the row readout time of 720 ns is achieved, which is two to five times smaller compared to the state-of-the-art.

A capacitive mismatch insensitive (CMI) multiplying digital to analog converter (MDAC) is proposed in this paper. MDAC requires only four clock phases for 2-bit conversion along with minimal use of circuit components. The reduction in number of clock cycles and improvement in speed is observed at the architecture level as well as circuit level compared to most of the circuits reported in literature. The CMI MDAC is designed and fabricated in AMS 350 nm CMOS process using 3.3 V power supply. The MDAC occupies an area of 70 mu mathrm{m}times 150 mu mathrm{m}. It requires only 240 ns to obtain the residue voltage and consumes 169.5 mu mathrm{W} of power. The proposed MDAC will result in an area efficient and high resolution readout when used in column-parallel cyclic ADC in CMOS image sensors.