Methodology of Gate Voltage Selection for Power Loss Manipulation of Power Semiconductor Device

Power loss manipulation is popularly used to control the junction temperature swing and hence, enhance reliability of power semiconductor devices (PSDs). Gate voltage control to drive the PSD in saturation region provides flexibility to control power losses. However, intermittent saturation region operation is not possible for commercially available gate drivers with desaturation protection. This paper proposes a methodology to select gate voltage range for loss manipulation of PSD. The objective of the proposed methodology is to select minimum value of gate voltage to ensure wide range of power loss modulation and thereby, enhanced lifetime. The proposed methodology considers the effect of parameter variation on gate voltage selection and avoids false triggering of desaturation protection during power loss manipulation. The simulation studies are carried out to validate the proposed method. The efficacy of proposed method is also validated experimentally on a 350W dc-dc boost converter prototype.