Analytical Modeling of Time Interval Error in CMOS Inverters in presence of Supply and Ground Variations

This paper proposes a method to estimate the Time Interval Error (TIE) and jitter in CMOS inverters when Power Supply Noise (PSN) and Ground-Bounce Noise (GBN) are present in the circuit. For that, an analytical expression of TIE and jitter are derived based on the input-output relationship of the inverter circuit, considering the effect of noise. Various examples are presented that support the validity of the proposed method. These examples include diverse experiments considering different parameters and different technology nodes. The results obtained from the simulations using a SPICE base simulator are compared with the ones obtained using the analytical modeling. The different technology nodes of United Microelectronics Corporation (UMC) are used here. Also, the measurement results obtained from the experiments using CMOS inverter integrated circuit (IC) are compared with the proposed analytical modeling. The results obtained using the proposed analytical approach are in congruence with those obtained using the SPICE-based simulator as well as from measurements.