12-Bit SAR ADC Design in SCL 180 nm for Sensor Interface Applications

A high-resolution analog-to-digital converter (ADC) is presented in this paper for application in sensor signal conditioning circuits. Based on the requirements of low complexity, low speed of operation, and moderate resolution, successive approximation register (SAR) ADC is most suitable. All the sub-circuits, i.e. comparator, sample and hold (with bootstrapped switching technique), SAR logic, and differential charge scaling digital-to-analog converter (DAC) circuits are designed, simulated, and verified using Cadence Virtuoso with SCL 180�nm PDK. The proposed design achieved 1.1 MS/s for 12-bit resolution with SDNR and ENOB of 73.54�dB and 11.92 bits, respectively. � The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2024.