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Modeling of Channel Hot Electron Degradation in n-MOSFETs
Journal
Proceedings of 2022 IEEE 16th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022
Date Issued
2022-01-01
Author(s)
Thakor, Karansingh
Diwakar, Himanshu
Mahapatra, Souvik
Abstract
Sentaurus TCAD is enabled and used to model the time kinetics of Channel Hot Electron Degradation (CHED) in n-channel MOSFETs. The impact of stress gate (VG) and drain (VD) bias and temperature (T) is studied on devices having various gate length (LG) and oxide thickness (TOX). Measured data from devices having different LG, TOX and junction structure are modeled using TCAD, when CHED is solely due to generated traps at the overlap and channel regions. In some devices, electron trapping and generated traps in the spacer also contributes, these are handled by a suitable compact model.