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BAT Framework Modeling of Dimension Scaling in FinFETs and GAA-SNS FETs
Journal
Recent Advances in PMOS Negative Bias Temperature Instability: Characterization and Modeling of Device Architecture, Material and Process Impact
Date Issued
2021-01-01
Author(s)
Mahapatra, Souvik
Parihar, Narendra
Choudhury, Nilotpal
Tiwari, Ravi
Samadder, Tarun
Abstract
In this chapter, the BAT framework presented in Chap. 4 through Chap. 6 is used to analyze and model the impact of device dimension scaling on NBTI in Silicon and Silicon Germanium channel FinFETs and Silicon channel GAA-SNS FETs with RMG HKMG gate insulator stack. The modeling is done on ultra-fast measured NBTI time kinetics in devices having different fin or sheet dimensions (length and width). The scaling of device dimensions changes the mechanical stress-induced compressive strain in the channel, which is verified using TCAD simulations. This impacts the magnitude of NBTI and its voltage dependence. Different manifestations are observed for the (110) sidewall dominated FinFETs and (100) top surface dominated GAA-SNS FETs. The observed differences are explained using band structure calculations. The impact of dimension scaling on the extrapolated EOL degradation under use conditions is determined by the calibrated BAT framework.