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BAT Framework Modeling of RMG HKMG GAA-SNS FETs
Journal
Recent Advances in PMOS Negative Bias Temperature Instability: Characterization and Modeling of Device Architecture, Material and Process Impact
Date Issued
2021-01-01
Author(s)
Choudhury, Nilotpal
Samadder, Tarun
Southwick, Richard
Zhou, Huimei
Wang, Miaomiao
Mahapatra, Souvik
Abstract
In this chapter, the BAT framework presented in Chaps. 4–6 is used to analyze and model the measured NBTI time kinetics in Silicon channel GAA-SNS FETs with RMG HKMG gate insulator stack. The ultra-fast measured stress and recovery data at different stress bias and temperature are modeled in devices having different sheet dimensions (length and width). The changes in voltage acceleration and temperature activation for changes in the sheet dimensions are modeled. The calibrated BAT framework is used to determine the impact of dimension scaling on the extrapolated EOL degradation under use condition.
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