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Analytical model based estimation of line edge roughness induced V<inf>T</inf> variability in nanowire FETs
Journal
Solid-State Electronics
ISSN
00381101
Date Issued
2022-11-01
Author(s)
Inge, Shashank V.
Jain, Agam
Rawat, Amita
Ganguly, Udayan
Abstract
The line edge roughness (LER) is one of the most dominant sources of variability in sub 10 nm technology node devices such as FinFET and Nanowire FET (NWFET). Earlier, analytical models of LER based threshold voltage (VT) variability on FinFET have been comprehensively explored. However, the analytical modeling front for NWFET is still an open challenge. Specifically, the previous FinFET inspired analysis used a cross-sectional area-equivalent circular diameter as effective diameter (Deff). The Deff defines the local VT for a cross-section that enables a percolation based VT estimation for the NWFET. In this work, we show that minimum local diameter (Dmin) is a better predictor. Dmin captures the quantum confinement locally more accurately in the highly scaled NWFETs of interest to enable accurate percolation. The model is tested for LER infused NWFET structures and shows an excellent match against the well-calibrated Sentaurus TCAD deck with the RMS error less than 1.5 mV. The model is 5×105 times computationally efficient in comparison to conventional TCAD simulations. Moreover, the proposed Dmin based analytical model is 2.3× better in terms of accuracy and 10× faster as opposed to the state-of-the-art (i.e. Deff based model). Such analytical models can be integrated in BSIM CMG platform to enable device scaling study and its impact on circuit level performance predictions.
Volume
197
Subjects