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Erratum: High-Performance 32-Bit Parallel Hybrid Adder Design Using RNS and Hybrid PTL/CMOS Logic (Journal of Circuits, Systems and Computers (2022) 31:11 (2250200) DOI: 10.1142/S0218126622502000)
Journal
Journal of Circuits, Systems and Computers
ISSN
02181266
Date Issued
2022-12-01
Author(s)
Khairnar, Avadhoot
Chauhan, Bhavuk
Sharma, Geetanjali
Joshi, Amit M.
Abstract
The new aliation has been added for the author, Ms. Geetanjali Sharma, which is, Maharaja Surajmal Institute of Technology, New Delhi. Ms. Geetanjali Sharma is a part-Time research scholar at the Malaviya National Institute of Technology in Jaipur, and she only listed this as her aliation in the published article. She also works as an Assistant Professor at the Maharaja Surajmal Institute of Technology in New Delhi, but this was not listed as an aliation in the published article. Now, she wants this also to be included as an aliation corresponding to her name due to professional commitment.