Agarwal, Harshit

In this article, we present a novel deep learning (DL) framework that fully automates the parameter extraction process for the BSIM-CMG unified model for advanced semiconductor devices. The framework seamlessly integrates with the BSIM-CMG model, making it applicable to diverse advanced devices such as GAA nanosheets, nanowire FETs, and FinFETs. Unlike existing approach involving DL for parameter extraction, the proposed framework combines physics-driven parameter initialization and data-driven DL enhancing the computational efficiency and making it easy to implement. It leverages the BSIM-CMG model's versatility for initial parameter estimation, the efficiency of DL algorithms for model parameter prediction, and the adaptability to various device geometries and configuration. The framework has been successfully validated with extensive numerical simulations and experimental data from 14-nm FinFET device with varying channel widths, 12-nm nanosheet, and 24-nm nanowire FET.

We present a new compact model of a perpendicular spin-transfer-torque (STT) magnetic tunnel junction (MTJ). Previous studies on STT-MTJs have either focused on solving the Landau-Lifshitz-Gilbert (LLG) equation or utilizing critical current-based macro models. However, the LLG approaches are too complex for large circuit simulations, while the macro models fail to capture the underlying magnetization physics. In this work, we propose a semiphysical and computationally efficient compact model that accurately represents the time-dependent magnet moment and resistance. To validate our model, we compare it with various experimental data and LLG-based STT-MTJ model. The model demonstrates geometry dependence and temperature dependence. Furthermore, we develop a continuous switching probability model to effectively track the probabilities of states under arbitrary waveforms.

Space charge modulation (SCM), that is, the increase of charge carriers in the drift region, modulates carrier concentration in the drift region, which results in conductivity modulation (also known as the expansion effect) of laterally double-diffused metal oxide semiconductor (LDMOS) transistors. In this work: 1) a compact model for conductivity modulation is presented. Since conductivity modulation also causes a change in internal node voltage ( $\textit{d}_{\textit{i}}$ ), therefore physics in the impact ionization model of drift region which accurately captures the change in node voltage is also included; 2) an improved model of impact ionization for the intrinsic region of LDMOS transistors ( $\textit{d}_{\textit{i}}$ ) is discussed and validated across a high drain voltage for different gate voltages; 3) the topology of the substrate current flow has been modified, in accordance with the device physics; and 4) finally, this work also includes the improved model of the impact ionization to capture the body bias effect in LDMOS transistors. The new model is extensively validated with the experimental and TCAD data. The research aims to enhance the industry-standard Berkeley short-channel IGFET model-bulk (BSIM-BULK) model, ensuring compatibility with SPICE simulators.

In this work, we discuss the impact of the ferroelectric polarization gradient (g) and viscosity coefficient (ρ) on the NCFET circuit. First, we examine the effect of g in the nmos and pmos transfer characteristics and VTC of the inverter circuit. Then, we examine low and high-frequency switching behavior by varying the ρ which is considered as the resistance of polarization switching. The operation of negative capacitance (NC) FET is examined at megahertz (MHz) and gigahertz (GHz) frequencies. We find that the dc and transient performance of NC-based circuits are strongly dependent on g and ρ respectively. We also show that at low ρ, the polarization state of the ferroelectric (FE) layer lies within the NC region while large ρ may bias the FE layer to positive capacitance (PC) region leading to performance degradation.

Nanosheet gate-all-around transistors are analyzed for RF applications using calibrated TCAD simulations. The effects of stack spacing and number of stacks on device performance are studied and a substack design for improved RF performance is proposed. The novel substack design can improve cut-off frequency ( ${F}_{{t}}$ ) by 10% and minimum number of substacks and minimum substack spacing should be used.

This brief presents a compact model to capture the major difference between high-voltage (HV) and low-voltage MOSFETs, i.e., the carrier velocity saturation effect in the drift region of HV MOSFETs. We discuss the numerical and behavioral issues that can arise in SPICE simulations with the existing current-dependent formulation in Berkeley-Short-Channel-IGFET model (BSIM) for HV transistors. We then demonstrate how a voltage-dependent formulation can mitigate them without losing simplicity and accuracy. We also validate the proposed model against experimental data of HV transistors.

A ferroelectric based electrostatic doping (Fe-ED) technique is proposed, as the alternative to chemical doping, providing non-volatile and programmable free electrons and holes for nanoscale devices. We show that Fe-ED achieves non-volatility and reconfigurability via the ferroelectric film inserted into the polarity gate, producing the reconfigurable nanosheet FETs (NSFETs) without the requirement of a constant bias. Thanks to the naturally formed lightly doped drain structures and the extremely high doping concentration over cm-3 in source/drain (S/D) regions, Fe-ED NSFETs exhibit the promising potential benefits for device scaling including the improved subthreshold swing, the suppressed drain-induced barrier lowering, and the ultralow S/D region resistance. Our study suggests a promising doping strategy of Fe-ED for versatile reconfigurable nanoscale transistors and highly integrated circuits.

We propose a compact model for nanosheet FETs that take the effects of quantum confinement into account. The model captures the nanosheet width and thickness dependence of the electrostatic dimension, density of states, effective mass, subband energies, and threshold voltages and includes them in the charge calculation, resulting in an accurate terminal charge and current characteristics. The model has been implemented using Verilog-A in the BSIM-CMG framework for all simulations. It has been validated with band-structure calculation-based TCAD simulations as well as measured data. We have also highlighted the significance of quantum mechanical effects on analog and RF performance of the device.

Social media holds the power to influence a significant change in the population. Through social media, people all around the world can connect and share their views. However, this social space is now infected due to the infiltration of fraudulent, obscene, fake and possibly, influential media. According to a UNESCO report, prevalence of fake news and deepfake content possess the potential of spreading fake propaganda and can lead to political and social unrest. Trust on social media is an emerging problem and there is an urgent need to address the same. There has been some research around approaches that detect fake news and deepfakes, however, identification of the source of these deepfakes posted on social media platforms is an equally important but relatively unexplored challenge. This paper proposes a novel Deepfake Source Identification (DeSI) algorithm that identifies the sources of deepfakes posted on Twitter. The proposed DeSI algorithm allows for two input modalities - text and images. We rigorously test our algorithm in both constrained and unconstrained experimental setups and report the observed results. In the constrained setting, the algorithm correctly identifies all the deepfake tweets as well their sources. The complete framework is further encased in a web portal to facilitate intuitive use and analysis of the results.

Flexible resistive random access memory (RRAM) devices with biomaterial gelatin and ultrathin HfOx hybrid bilayer dielectric exhibiting excellent resistive switching (RS) behavior are demonstrated. The fabricated devices show a very high memory window of greater than $10^{{5}}$ and data retention of $10^{{4}}$ s without any degradation in a pristine state. Moreover, to investigate the mechanical stability of the hybrid bilayer film and variation in switching performance upon bending was studied by bending the devices at a 12-mm radius followed by 7 mm. Even after this extreme bending, the device maintained the memory window of $10^{{5}}$ without any degradation in data retention, indicating excellent electromechanical stability of the device. Furthermore, a simple mathematical model of the RRAM device was used to simulate these devices with the help of our experimental data and the ${I}$ - ${V}$ equations. The developed model shows excellent accuracy with a relative root mean square (RMS) error of less than 5%, which can prove to be an excellent tool for the simulation of circuits and systems based on these RRAMs.