Tripathi, Jai Narayan

This paper proposes a method to estimate the Time Interval Error (TIE) and jitter in CMOS inverters when Power Supply Noise (PSN) and Ground-Bounce Noise (GBN) are present in the circuit. For that, an analytical expression of TIE and jitter are derived based on the input-output relationship of the inverter circuit, considering the effect of noise. Various examples are presented that support the validity of the proposed method. These examples include diverse experiments considering different parameters and different technology nodes. The results obtained from the simulations using a SPICE base simulator are compared with the ones obtained using the analytical modeling. The different technology nodes of United Microelectronics Corporation (UMC) are used here. Also, the measurement results obtained from the experiments using CMOS inverter integrated circuit (IC) are compared with the proposed analytical modeling. The results obtained using the proposed analytical approach are in congruence with those obtained using the SPICE-based simulator as well as from measurements.

This paper presents an efficient method for the analysis of power supply induced jitter using machine learning techniques in the presence of supply noise for CMOS inverter circuits. In the proposed hybrid approach, knowledge-based neural network and deep belief neural network produce reasonably accurate jitter response while providing an efficient training using training data extracted from both analytical models as well as a circuit simulator. The proposed model can also handle varying inputs without re-training the network's parameters.

This work presents an efficient approach to estimate power supply and ground-bounce induced jitter for a voltage-mode driver (VMD) circuit driving long transmission lines. Considering the spatial and temporal components of long transmission lines, a semi-analytical method is used to determine jitter at the differential output response of VMD. It uses slope-based method to model the timing uncertainty and requires only one-bit simulation for the estimation of jitter. The results obtained from the proposed method are compared with the results obtained using SPICE based simulator to validate the proposed methodology for estimating jitter.

The past decade has witnessed a tremendous reduction in the feature size from the deepsubmicron to the advanced nano-scale CMOS devices. In nanoscale devices based high-speed systems, the budgeting of jitter due to supply fluctuations is one of the major performance bottlenecks while designing integrated circuits (ICs). In this paper, an accurate and efficient method to analyse power supply induced jitter (PSIJ) in CMOS N-stage inverters is developed using the estimation-by-inspection method. Based on the Indefinite Admittance Matrix, a reduced two-port network is developed for a multiple-input circuit, considering the presence of the supply/bulk/ground sources. The closed-form expressions of the PSIJ have been evaluated for a single and N-stages CMOS inverter chain. The expression is also valid for the PSIJ analysis at any intermediate stage of the N-stage chain. For validation purpose, the circuits are designed in a standard 28 nm CMOS technology with VDD of 1 V. The analytical results are compared with the simulation and the experiments. The maximum mean percentage error for EDA simulation and experimentally measured results are 2.4% and 13%, respectively. The proposed analysis is compared with some of the existing PSIJ modelling techniques and shows a significant improvement in speed-up factor and error percentage.

Background: Improvements in the financing of healthcare services are important for developing countries like India to make progress towards universal health coverage. Inpatient-care contributes to a big share of total health expenditure in India. India has a mixed health-system with a sizeable presence of private hospitals. Existing studies show that out-of-pocket expenditure (OOPE) incurred per hospitalisation in private hospitals was greater than public facilities. But, such comparisons have not taken into account the healthcare spending by government. Methods: For a valid comparison between public and for-profit private providers, this study in Indian state of Chhattisgarh assessed the combined spending by government and households per episode of hospitalisation. The supply-side and demand-side spending from public and private sources was taken into account. The study used two datasets: a) household survey for data on hospital utilisation, OOPE, cash incentives received by patients and claims raised under publicly funded health insurance (PFHI) schemes (n = 903 hospitalisation episodes) b) survey of public facilities to find supply-side government spending per hospitalisation (n = 64 facilities). Results: Taking into account all relevant demand and supply side expenditures, the average total spending per day of hospitalisation was INR 2833 for public hospitals and INR 6788 for private hospitals. Adjusted model for logarithmic transformation of OOPE while controlling for variables including case-mix showed that a hospitalisation in private hospitals was significantly more expensive than public hospitals (coefficient = 2.9, p < 0.001). Hospitalisations in private hospitals were more likely to result in a PFHI claim (adjusted-odds-ratio = 1.45, p = 0.02) and involve a greater amount than public hospitals (coefficient = 0.27, p < 0.001). Propensity-score matching models confirmed the above results. Overall, supply-side public spending contributed to 16% of total spending, demand-side spending through PFHI to 16%, cash incentives to 1% and OOPE to 67%. OOPE constituted 31% of total spending per episode in public and 86% in private hospitals. Conclusions: Government and households put together spent substantially more per hospitalisation in private hospitals than public hospitals in Chhattisgarh. This has important implications for the allocative efficiency and the desired public-private provider-mix. Using public resources for purchasing inpatient care services from private providers may not be a suitable strategy for such contexts.

In this paper, a novel methodology for variability analysis of CMOS circuits is presented. An automated framework is proposed that uses swarm intelligence based optimization technique, namely particle swarm optimization algorithm, to estimate the worst-case variability bounds of the system response. The efficacy of the proposed method is illustrated by performing the variability in phase noise of a 2.4 GHz CMOS LC tank RF oscillator. The proposed methodology is investigated and validated by comparing it with the conventional Monte Carlo simulations technique. For this case study, the proposed method is found to be significantly time-efficient.

This study discusses and introduces the impact of variability on power supply-induced jitter in integrated circuits. It presents an analytical approach to model timing uncertainty in the output response of CMOS inverters due to process variations as well as power supply noise. The proposed theory is verified with both simulation and measurement. The proposed approach is not only limited to jitter estimation but it can also be used to analyze the variability issues in CMOS circuits.

In this paper, an efficient method for analysis of power supply induced jitter (PSIJ) is presented. In the proposed approach, the noise spectrum for an arbitrary noise is generated via Fourier series and the knowledge-based neural network (KBNN) is generated to accurately predict the response of PSIJ transfer function (PSIJTF) using the training data extracted from two types of models, analytical closed-form expressions as well as computationally expensive circuit simulator. Employing KBNN based transfer function model with the noise spectrum gives reasonably accurate estimation of PSIJ for multiple input noises. A case study with 32nm CMOS technology is presented to demonstrate the validity of the proposed model compared to a circuit simulator.

This paper presents the development of nonlinear dynamic behavioral model of the IO buffer circuits' pre-driver stage. A time delay neural network structure is developed to model the electrical circuit behavior of pre-driver in order to identify the mathematical relationship between the input voltage and output switching timing signals under power supply voltage variation. Therefore, the pre-driver model is combined with the last-stage output buffer model to illustrate the improved accuracy of the proposed modelling for capturing the supply variation induced jitter. For instance, the proposed modeling approach presents jitter peak-to-peak error about 9.84% while IBIS like model presents 88% when compared to reference transistor level model.

This paper discusses the performance of various regression-based machine learning approaches for the variability analysis of integrated circuits. The considered approaches include Support Vector Machine, Least Square-Support Vector Machine, Random Forest and Gaussian process regression. The efficacies of these approaches are demonstrated using two circuit examples- a CMOS LC oscillator and a low-noise amplifier. Here, the performance of all the approaches in the presence and absence of numerical noise is compared to the state-of-the-art methods such as sparse Polynomial Chaos expansion and Monte Carlo analysis to provide a complete overview. This study guides the readers to choose an appropriate learning model for similar applications of variability analysis of the integrated circuits.